Challenges in physical chip design

Chip industry obeys a number of laws, various kinds of laws. Mathematical laws if accurate models can be formulated, physical laws, especially solid state physics, obtained by observation and induction, chemical laws pertinent for the manufacturing processes, economical and judicial laws that concern such industries. These laws still hold true, although technology has come a long way since they were formulated. Obviously, modern technologies require a completely different design flow. Homogeneous processors do not benefit much from parts of a traditional flow. The emphasis should be more on modeling applications as networks of communicating processes in a suitable specification language. Equally important is reuse of specification software, considering the short life spans of integrated circuits and the demand for short paths to the market. General multilayer designs require complete new layout synthesis tools. Placement is obsolete and even floorplan design for each layer is not adequate because of the strong geometrical constraints. Wire planning will be more of a must, but has to acquire a more precise meaning in this application. The challenges posed by the unavoidable escape routes, to break free from the confinements of conventional large scale integration methodologies, is the topic of this paper.