Title :
A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer
Author :
Chae, J. ; Lee, S. ; Aniya, M. ; Takeuchi, S. ; Hamashita, K. ; Hanumolu, P.K. ; Temes, G.C.
Author_Institution :
Sch. of EECS, Oregon State Univ., Corvallis, OR, USA
Abstract :
A wideband ΔΣ ADC using a novel double-sampling scheme with a single set of capacitors and a dynamic embedded-adder quantizer is presented. The proposed quantizer eliminates static currents in the adder of a low-distortion architecture. Fabricated in 0.18 μm CMOS process, the prototype chip operates with a 320 MHz sampling frequency and achieves 63 dB SNDR in a 20 MHz signal band while consuming 16 mW power.
Keywords :
CMOS integrated circuits; adders; analogue-digital conversion; CMOS process; analog-to-digital converter; bandwidth 20 MHz; capacitor; double-sampling scheme; dynamic embedded-adder quantizer; frequency 320 MHz; low-distortion architecture; power 16 mW; size 0.18 mum; static current; wideband ΔΣ ADC; Adders; Bandwidth; Capacitors; Modulation; Noise; Power demand; Switches;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-5758-8
DOI :
10.1109/CICC.2010.5617594
