Analysis of architectures for fault-tolerant computation

The paper develops computational models to examine the relative viability of von Neumann, Very Long Instruction Word (VLIW), and dataflow architectures for fault-tolerant applications requiring modular redundancy. Analytic machine execution cycle equations are developed for each class of machine with respect to varying amounts of voting overhead and granularity. Shared memory access as a function of memory bandwidth and program decomposition of the application´s algorithm are attributes that are varied for each architecture. Cycle time and technology considerations are then integrated to reflect the actual task execution time. The models and analysis provide a framework for evaluating candidate architectures for fault-tolerant voting applications