The design of a GaAs micro-supercomputer

Author

Mudge ; Brown, Richard B. ; Birmingham, W.P. ; Kayssi, A.I. ; Lomax, R.J. ; Sakallah, Karem A.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI

Volume

i

fYear

1991

fDate

8-11 Jan 1991

Firstpage

421

Abstract

The paper is an overview of the architecture, technology and CAD tools used in the design of an experimental 250 MHz `micro-supercomputer´ which is being designed for a sustained performance of 170 MIPS. The system will include a gallium arsenide processor which executes the MIPS instruction set and a two-level cache memory system, packaged on a multi-chip module. The risk in undertaking this project is minimized by using existing but advanced GaAs technology (GaAs MESFET enhancement/depletion direct-coupled FET logic (E/D DCFL)), by building needed CAD tools on top of commercial tools, and by using a standard instruction-set architecture

Keywords

III-VI semiconductors; buffer storage; field effect integrated circuits; gallium arsenide; instruction sets; microprocessor chips; storage management chips; 170 MIPS; 250 MHz; 32 bit; MIPS instruction set; FD-TLM simulation; GaAs compiler; GaAs micro-supercomputer; GaAs processor chip; GaAs technology; semiconductor; standard instruction-set architecture; timing analysis; two-level cache memory; Aging; Buildings; Cache memory; Delay; Design automation; Gallium arsenide; Logic testing; Microprocessors; Packaging; Supercomputers;

fLanguage

English

Publisher

ieee

Conference_Titel

System Sciences, 1991. Proceedings of the Twenty-Fourth Annual Hawaii International Conference on

Conference_Location

Kauai, HI

Type

conf

DOI

10.1109/HICSS.1991.183912

Filename

183912