Title :
Overview of the PIPE processor implementation
Author :
Farrens, Matthew K. ; Pleszkun, Andrew R.
Author_Institution :
Div. of Comput. Sci., California Univ., Davis, CA, USA
Abstract :
PIPE (parallel instruction with pipelined execution) processor is a 32-bit pipelined single chip processor with a simplified load-store instruction set, a five stage pipeline, a two-cycle ALU, and the following unique features: architectural queues; delayed branch scheme; sophisticated instruction cache, branch register file; subroutine call support; and branch queues. The nMOS implementation and lessons learned from it are discussed
Keywords :
MOS integrated circuits; buffer storage; computer architecture; microprocessor chips; pipeline processing; 32-bit pipelined single chip processor; PIPE processor; architectural queues; branch queues; branch register file; delayed branch scheme; five stage pipeline; instruction cache; load-store instruction set; parallel instruction with pipelined execution; subroutine call support; Algorithms; Clocks; Computer architecture; Computer science; Delay; MOS devices; Pipelines; Processor scheduling; Reduced instruction set computing; Very large scale integration;
Conference_Titel :
System Sciences, 1991. Proceedings of the Twenty-Fourth Annual Hawaii International Conference on
Conference_Location :
Kauai, HI
DOI :
10.1109/HICSS.1991.183913
