Title :
Hector-a hierarchically structured shared memory multiprocessor
Author :
Vranesic, Z.G. ; Stumm, M. ; Lewis, D.M. ; White, R.
Author_Institution :
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
Abstract :
Hector is a shared-memory multiprocessor with a hierarchical interconnection structure that has three important advantages. First, it uses only short transmission lines and allows implementations with simple, modular hardware. This makes it scalable to match the needs of tomorrow´s high speed microprocessors. Second, the cost and the overall bandwidth of the structure grow linearly with the number of processing modules. This makes Hector expandable to moderate sizes of up to 256 PMs, yet allows small-scale systems at a low cost. Finally, the cost of a memory access grows incrementally with the distance between the processor and memory location. This allows single threaded applications, applications with a small degree of parallelism, and applications with a high degree of locality in their memory accesses to exploit the low cost of localized memory accesses
Keywords :
computer interfaces; multiprocessor interconnection networks; parallel architectures; Hector; hierarchical interconnection structure; inter-ring controller; localized memory accesses; modular hardware; shared-memory multiprocessor; short transmission lines; single threaded applications; station bus interface; station controller; Backplanes; Bandwidth; Costs; Hardware; Integrated circuit interconnections; Logic circuits; Microprocessors; Multiprocessor interconnection networks; Power generation economics; Transmission lines;
Conference_Titel :
System Sciences, 1991. Proceedings of the Twenty-Fourth Annual Hawaii International Conference on
Conference_Location :
Kauai, HI
DOI :
10.1109/HICSS.1991.183914