• DocumentCode
    2791063
  • Title

    Full-chip, three-dimensional, shapes-based RLC extraction

  • Author

    Shepard, K.L. ; Sitaram, D. ; Yu Zheng

  • Author_Institution
    Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
  • fYear
    2000
  • fDate
    5-9 Nov. 2000
  • Firstpage
    142
  • Lastpage
    149
  • Abstract
    In this paper, we report the development of the first commercial full-chip, three-dimensional, shapes-based, RLCK extraction tool, developed as part of a university-industry collaboration. The technique of return-limited inductances is used to provide a sparse, frequency-independent inductance and resistance network with self-inductances that represent sensible "nominal" values in the absence of mutual coupling. Mutual inductances are extracted for accurate noise analysis. The tool, Assura RLCX, exploits high-capacity scan-band techniques and disk caching for inductance extraction as an extension to Cadence\´s existing Assura RCX extractor.
  • Keywords
    circuit CAD; inductance; Assura RLCX; RLC extraction; RLCK extraction tool; disk caching; frequency-independent inductance and resistance network; high-capacity scan-band; inductance extraction; noise analysis; self-inductances; Circuit noise; Delay; Equations; Frequency; Immune system; Inductance; Integrated circuit interconnections; Propagation losses; Timing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • ISSN
    1092-3152
  • Print_ISBN
    0-7803-6445-7
  • Type

    conf

  • DOI
    10.1109/ICCAD.2000.896464
  • Filename
    896464