Hierarchical interconnect circuit models

The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable proportions. Interconnect extraction tools employ hierarchy to manage complexity, but this hierarchy is discarded via eliminating far away coupling terms when the equivalent ARC circuits are Formed. The increasing dominance of capacitance coupling along with the emergence of on chip inductance, however, makes the composite effect of far-away couplings increasingly evident. Even if newly enforced design rules and practices will ultimately obviate the need for modeling these couplings for design verification, some approximation of the "exact" solution is required to validate these rules. This paper proposes an efficient hierarchical equivalent circuit representation of interconnect parasitics that utilizes the efficient hierarchical long-distance modeling already existing within extractors. Results from a prototype simulator based on these hierarchical models demonstrate the simulation inaccuracy incurred when the faraway coupling terms are ignored. Such a form of interconnect modeling may provide the key to hierarchical modeling of electro-magnetic interactions between large components on future gigascale systems.