DocumentCode :
2791337
Title :
Effective partition-driven placement with simultaneous level processing and global net views
Author :
Ke Zhong ; Dutt, S.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Illinois Univ., Chicago, IL, USA
fYear :
2000
fDate :
5-9 Nov. 2000
Firstpage :
254
Lastpage :
259
Abstract :
In this paper we take a fresh look at the partition-driven placement (PDP) paradigm for standard-cell placement for wire-length minimization. The goal is to develop several new algorithms for incorporation into a PDP framework that can rectify the well-known drawbacks of traditional PDP (increasingly localized view of nets with increasing levels of the partitioning tree, min cut objective, inaccuracy and cost of terminal propagation (TP), irreversibility of move decisions), while preserving its considerable advantages (time efficiency, flexibility in accurately incorporating many optimization metrics, and flexibility in satisfying most constraints). We have developed several novel techniques within a PDP-based framework that yield the best wire-length results so far on all but two of the MONO benchmark suite. Our major innovations are: (1) simultaneous level partitioning (SLP) in which we partition the entire circuit globally in every level of the partitioning tree, across the current cutline(s); (2) cell gain computation based on a global or distributed view of entire nets (thus obviating TP) and on the bounding-box (BB) minimization of nets (as opposed to mincut in prior PDP); (3) move irreversibility tackled in a pest-processing phase via vertical and horizontal swaps. Empirical results indicate that our PDP algorithm SPADE (for Simultaneous level Partitioning with Distributed lie., global] nEt views) provides almost 202 better wirelength results than an internal version of "regular" PDP with min-cut based gains, 10.8% better than the previous best PDP method QUAD, 10.6% better than TimberWolf (TW) 7.0, 15.846 better than the state-of-the-art force-directed technique from U. Munich (termed FD-98 here), and 15.3% better than the multilevel placement technique Snap-On. Besides TW7.0, we are also the only ones to report results on the approximately 100 K-cell circuit golem3 (12.2% better than TW7.0). Our run times are quite reasonable.
Keywords :
circuit layout CAD; simulated annealing; global net views; min cut objective; partition-driven placement; simultaneous level partitioning; simultaneous level processing; standard-cell placement; terminal propagation; time efficiency; wire-length minimization; Circuits; Constraint optimization; Cost function; Crosstalk; Delay; Distributed computing; Minimization; Partitioning algorithms; Technological innovation; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
ISSN :
1092-3152
Print_ISBN :
0-7803-6445-7
Type :
conf
DOI :
10.1109/ICCAD.2000.896482
Filename :
896482
Link To Document :
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