DocumentCode
2791524
Title
7T SRAM enabling low-energy simultaneous block copy
Author
Okumura, Shunsuke ; Yoshimoto, Shusuke ; Yamaguchi, Kosuke ; Nakata, Yohei ; Kawaguchi, Hiroshi ; Yoshimoto, Masahiko
Author_Institution
Kobe Univ., Kobe, Japan
fYear
2010
fDate
19-22 Sept. 2010
Firstpage
1
Lastpage
4
Abstract
This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the conventional read-modify-write manner.
Keywords
SRAM chips; 7T SRAM; checkpoint data storage; low-energy simultaneous block copy; memory size 1 MByte; transactional memory; voltage 1.2 V; Clocks; Decoding; Energy consumption; Layout; Multicore processing; Random access memory; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Conference_Location
San Jose, CA
ISSN
0886-5930
Print_ISBN
978-1-4244-5758-8
Type
conf
DOI
10.1109/CICC.2010.5617629
Filename
5617629
Link To Document