A 32nm 0.5V-supply dual-read 6T SRAM

Author

Kuang, J.B. ; Schaub, J.D. ; Gebara, F.H. ; Wendel, D. ; Saroop, S. ; Nguyen, T. ; Fröhnel, T. ; Müller, A. ; Durham, C.M. ; Sautter, R. ; Lloyd, B. ; Robbins, B. ; Pille, J. ; Nassif, S.R. ; Nowka, K.J.

Author_Institution

Austin Res. Lab., IBM Corp., Austin, TX, USA

fYear

2010

fDate

19-22 Sept. 2010

Firstpage

1

Lastpage

4

Abstract

Dual read port SRAMs play a critical role in high performance cache designs, but stability and sensing challenges typically limit the low voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32nm metal-gate partially depleted (PD) SOI technology, for low-voltage applications. Hardware exhibits robust operation at 348MHz and 0.5V with a read and write power of 3.33 and 1.97mW, respectively, per 4.5KB active array with both read ports accessed at the highest activity data pattern. At a 0.6V supply, an access speed of 1.2GHz is observed.

Keywords

SRAM chips; cache storage; low-power electronics; silicon-on-insulator; dual read port SRAM; frequency 1.2 GHz; frequency 348 MHz; high performance cache design; low voltage operation; metal-gate partially depleted SOI technology; power 1.97 mW; power 3.33 mW; size 32 nm; voltage 0.5 V; voltage 0.6 V; Arrays; Clocks; Delay; Logic gates; Low voltage; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4244-5758-8

Type

conf

DOI

10.1109/CICC.2010.5617630

Filename

5617630