Technology-circuit co-design of asymmetric SRAM cells for read stability improvement

We present asymmetric SRAM cell design approaches to improve Read stability over conventional symmetric SRAM Cell. We show that selective threshold voltage control is more effective than adjusting transistor size for read stability improvement in an asymmetric SRAM cell. We implement statistical DC noise margin monitors and present the hardware measurement data as well as the DC/AC simulation data to support the claims.