• DocumentCode
    2791652
  • Title

    Mitigation of Single-and Multiple-Cycle-Duration SETs using Double-Mode-Redundancy (DMR) in Time

  • Author

    Kim, Jung E. ; Lin, Jimmy ; Mcmurchie, Larry ; Sechen, Carl

  • Author_Institution
    Dept. of Electr. Eng., Washington Univ., Seattle, WA
  • fYear
    2005
  • fDate
    5-12 March 2005
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    TMR-in-hardware is a traditional architectural solution to radiation hardening. Simple in concept, TMR-in-hardware incurs at least 3times power and area penalties over the unhardened singlet computation. In this paper we focus upon compute-intensive pipelined computations and present an efficient alternative - dual mode redundancy (DMR). DMR-in-time utilizes dual computation threads to detect an error. To correct an error DMR-in-time utilizes relatively small input and output queues for rolling back the computation to a known correct state. DMR-in-time incurs only a 2times decrease in throughput, requires no downtime for error correction, and has power requirements only marginally greater than the unhardened singlet computation
  • Keywords
    error correction; error detection; pipeline arithmetic; radiation hardening (electronics); redundancy; DMR in time; double-mode-redundancy in time; error correction; error detection; multiple-cycle-duration SET; radiation hardening; single-cycle-duration SET; Clocks; Delay; Error correction; Hardware; Logic; Power engineering computing; Registers; Single event transient; Throughput; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Aerospace Conference, 2005 IEEE
  • Conference_Location
    Big Sky, MT
  • Print_ISBN
    0-7803-8870-4
  • Type

    conf

  • DOI
    10.1109/AERO.2005.1559556
  • Filename
    1559556