DocumentCode
2791862
Title
Improving the proportion of at-speed tests in scan BIST
Author
Huang, Y. ; Pomeranz, I. ; Reddy, S.M. ; Rajski, J.
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear
2000
fDate
5-9 Nov. 2000
Firstpage
459
Lastpage
463
Abstract
A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors applied when the circuit operates as a sequential circuit, without using scan. These sequences can be applied at-speed, i.e., at the normal circuit clock speed. The objectives set for choosing the lengths of the functional sequences are to increase the number of vectors applied at-speed, and to reduce the number of settings of functional sequence lengths, without compromising the fault coverage achieved. The experimental results presented demonstrate that compared to earlier methods, the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.
Keywords
built-in self test; logic testing; at-speed tests; benchmark circuits; functional sequence; functional sequences; scan BIST; scan designs; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Design optimization; Frequency; Power dissipation; Sequential circuits; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-7803-6445-7
Type
conf
DOI
10.1109/ICCAD.2000.896514
Filename
896514
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