DocumentCode
2791920
Title
Diagnosis of interconnect faults in cluster-based FPGA architectures
Author
Harris, I. ; Tessier, R.
Author_Institution
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fYear
2000
fDate
5-9 Nov. 2000
Firstpage
472
Lastpage
475
Abstract
Fault diagnosis has particular importance in the context of field programmable gate arrays (FPGAs) because faults can be avoided by reconfiguration at almost no real cost. Cluster-based FPGA architectures, in which several logic blocks are grouped together into a coarse-grained logic block, are rapidly becoming the architecture of choice for major FPGA manufacturers. The high density interconnect found within clusters greatly complicates the problem of FPGA diagnosis. We propose a technique for the testing and diagnosis of cluster-based FPGA architectures. We present a hierarchical approach to define a set of FPGA configurations in which each fault is detectable, and each fault pair is differentiable. The cornerstone of this work is the concise expression of the distinguishing conditions of each fault pair. Experimental results demonstrate that nearly 100% fault coverage and diagnostic resolution are achieved with a low number of test configurations.
Keywords
fault diagnosis; field programmable gate arrays; logic testing; cluster-based FPGA architectures; diagnostic resolution; fault diagnosis; field programmable gate arrays; hierarchical approach; interconnect faults diagnosis; logic blocks; test configurations; Circuit faults; Circuit testing; Computer architecture; Costs; Fault detection; Fault diagnosis; Field programmable gate arrays; Integrated circuit interconnections; Logic devices; Reconfigurable logic;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-7803-6445-7
Type
conf
DOI
10.1109/ICCAD.2000.896517
Filename
896517
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