DocumentCode :
2792086
Title :
Don´t cares and multi-valued logic network minimization
Author :
Yunjian Jiang ; Brayton, R.K.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear :
2000
fDate :
5-9 Nov. 2000
Firstpage :
520
Lastpage :
525
Abstract :
We address optimizing multi-valued (MV) logic functions in a multi-level combinational logic network. Each node in the network, called an MV-node, has multi-valued inputs and single multi-valued output. The notion of don´t cares used in binary logic is generalized to multi-valued logic. It contains two types of flexibility: incomplete specification and non-determinism. We generalize the computation of observability don´t cares for a multi-valued function node. Methods are given to compute (a) the maximum set of observability don´t cares, and (b) the compatible set of observability don´t cares for each MV-node. We give a recursive image computation to transform the don´t cares into the space of local inputs of the node to be minimized. The methods are applied to some experimental multi-valued networks, and demonstrate reduction in the size of the tables that represent multi-valued logic functions.
Keywords :
combinational circuits; minimisation of switching nets; multivalued logic; observability; binary logic; incomplete specification; logic functions; multi-level combinational logic network; multi-valued logic network minimization; observability; recursive image computation; Circuit synthesis; Computer networks; Minimization methods; Multivalued logic; Observability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
ISSN :
1092-3152
Print_ISBN :
0-7803-6445-7
Type :
conf
DOI :
10.1109/ICCAD.2000.896525
Filename :
896525
Link To Document :
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