Deterministic test pattern generation techniques for sequential circuits

This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation algorithms. To be able to assess the effectiveness of the proposed techniques, we have developed a new ATPG system for sequential circuits, called ATOMS, and we have incorporated these techniques into the test generator ATOMS achieved very high fault coverages in a short amount of time for the ISCAS89 sequential benchmark circuits, demonstrating the effectiveness of these techniques on the test generation performance.