DocumentCode
2792148
Title
Which comes first: the architecture or the algorithm?
Author
Gropp, William
Author_Institution
Div. of Math. & Comput. Sci., Argonne Nat. Lab., IL, USA
fYear
1997
fDate
22-24 Oct 1997
Firstpage
13
Abstract
There is a constant tension between the designers of algorithms and architectures. Each designs for the other´s previous generation. Several factors are making this an increasingly inadequate approach. On the hardware side, the growing disparity between the performance of memory and CPU has pushed many architectures to hierarchical memories that reward significant data reuse (and punish algorithms that use data items a small number of times). On the algorithmic side, at least for a large class of algorithms in scientific computing, the emphasis on increasingly efficient algorithms, measured by the amount of work (floating point operations) per solution value, has led to algorithms that touch data only a few times. Further, algorithmic techniques that lead to adaptive methods (computing only with as much data as is required to accurately represent the solution) often lead to irregular or unpredictable accesses to memory. While these trends in architectures and algorithms are away from each other, there are other trends in algorithms that provide both a degree of greater memory locality without sacrificing algorithmic optimality. These are hierarchical methods, such as multigrid and general domain decomposition. These hierarchical methods place some requirements on architectures; primarily that there be no distinguished collection of processes/threads in a computation. Another opportunity in algorithms is the potential for exploiting split-phase or two-step operations
Keywords
algorithm theory; memory architecture; subroutines; CPU performance; adaptive methods; algorithmic optimality; algorithms; architectures; computation; data reuse; general domain decomposition; hardware; hierarchical memories; memory locality; memory performance; multigrid domain decomposition; processes; scientific computing; split-phase operations; threads; two-step operations; Algorithm design and analysis; Computer architecture; Computer science; Hardware; Laboratories; Mathematics; Memory architecture; Scientific computing; World Wide Web; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Innovative Architecture for Future Generation High-Performance Processors and Systems, 1997
Conference_Location
Maui, HI
ISSN
1537-3223
Print_ISBN
0-8186-8424-0
Type
conf
DOI
10.1109/IWIA.1997.670400
Filename
670400
Link To Document