Speculative resolution of ambiguous memory aliasing

Author

Sato, Toshinori

Author_Institution

Toshiba Microelectron. Eng. Lab., Kawasaki, Japan

fYear

1997

fDate

22-24 Oct 1997

Firstpage

17

Lastpage

26

Abstract

The ambiguous memory aliasing is proposed to be speculatively resolved. A load instruction is speculatively executed with load address prediction, and its dependent instructions are speculatively executed. A store instruction is also speculatively resolved with store address prediction, and its dependent instructions are speculatively executed. From the experimental evaluation, the author has found that this data speculation combining memory disambiguation with address prediction improves the performance of next-generation super-scalar processors by up to 21.0%

Keywords

multiprocessing systems; parallel processing; virtual storage; ambiguous memory aliasing; data speculation; dependent instructions; load address prediction; load instruction; memory disambiguation; speculative resolution; store address prediction; store instruction; super-scalar processors; Advertising; Hazards; IEEE services; Laboratories; Microelectronics; Out of order; Permission; Registers; Transistors; USA Councils;

fLanguage

English

Publisher

ieee

Conference_Titel

Innovative Architecture for Future Generation High-Performance Processors and Systems, 1997

Conference_Location

Maui, HI

ISSN

1537-3223

Print_ISBN

0-8186-8424-0

Type

conf

DOI

10.1109/IWIA.1997.670402

Filename

670402