Testing of iterative logic arrays

A method is presented to identify test vectors for iterative logic arrays (ILA). An ILA consists of several identical cells connected together in a regular configuration. The circuit regularity is exploited to regenerate the test vectors, applied at the boundary cells, within the array and thus propagate the test vectors to the entire array. This facilitates simultaneous testing of the entire circuit. The method covers a wide range of regular array structures like adders, multipliers, and interconnection networks