Improved multiplier of CSD used in digital signal processing

Author

Chen, Lei ; Tian, Xiao-Yan ; Zhao, Xiao-Jun

Author_Institution

Coll. of Electron. & Inf. Eng., Hebei Univ., Baoding

Volume

5

fYear

2008

fDate

12-15 July 2008

Firstpage

2905

Lastpage

2908

Abstract

Multiplication is the basic operation unit in digital signal processing. Its speed determines the performance of the system, such as CUP, DSP, digital filter and so on. CSD (canonical signed-digit) code is characterized by low resource occupation, high efficiency and high parallel speed. It can efficiently reduce the operation load and time consumption. In addition, this design integrates the Wallace tree addition and carry look-ahead addition with the operation unit of CSD, the former can reduce the addition amount, then the latter improved the operation speed, thus which has further improved the performance of the multiplication operation. At last, we realized the verification by FPGA.

Keywords

field programmable gate arrays; multiplying circuits; signal processing; FPGA; Wallace tree addition; canonical signed-digit code; digital signal processing; low resource occupation; Algorithm design and analysis; Cybernetics; Digital arithmetic; Digital filters; Digital signal processing; Educational institutions; Field programmable gate arrays; Hardware; Machine learning; Table lookup; CSD; FPGA; Wallace tree adder; carry look-ahead adder;

fLanguage

English

Publisher

ieee

Conference_Titel

Machine Learning and Cybernetics, 2008 International Conference on

Conference_Location

Kunming

Print_ISBN

978-1-4244-2095-7

Electronic_ISBN

978-1-4244-2096-4

Type

conf

DOI

10.1109/ICMLC.2008.4620904

Filename

4620904