Title :
A power IC technology with excellent trench isolation and p-LDMOS transistor through tapered TEOS field oxides
Author :
Kim, Sang Gi ; Kim, Jongdae ; Song, Q. Sang ; Koo, Jin Gun ; Kim, Dae Yong ; Cho, Kyoung-Ik
Author_Institution :
Lab. of Micro-Electron. Technol., Electron. & Telecommun. Res. Inst., Taejon, South Korea
Abstract :
A smart PIC technology with the reproducible tapered TEOS oxide has been proposed to reduce the fabrication process steps and obtain p-LDMOS with low on-resistance. Several process steps could be reduced, compared to the conventional process. With a similar breakdown voltage (5% reduction), the on-resistance was improved by 35% or more with the proposed structure
Keywords :
MOS integrated circuits; dielectric thin films; electric breakdown; electric resistance; isolation technology; power MOSFET; power integrated circuits; SiO2-Si; breakdown voltage; fabrication process steps; on-resistance; p-LDMOS; p-LDMOS transistor; power IC technology; process steps; reproducible tapered TEOS oxide; smart PIC technology; trench isolation; Annealing; CMOS process; CMOS technology; Etching; Fabrication; Filling; Isolation technology; Low voltage; Plasma displays; Power integrated circuits;
Conference_Titel :
Power Semiconductor Devices and ICs, 1999. ISPSD '99. Proceedings., The 11th International Symposium on
Conference_Location :
Toronto, Ont.
Print_ISBN :
0-7803-5290-4
DOI :
10.1109/ISPSD.1999.764119
