DocumentCode :
2794543
Title :
Two-level soft error vulnerability prediction on SMT/CMP architectures
Author :
Duan, Lide ; Peng, Lu ; Li, Bin
Author_Institution :
Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA
fYear :
2011
fDate :
6-8 Nov. 2011
Firstpage :
78
Lastpage :
78
Abstract :
Architectural Vulnerability Factor (AVF) [3] quantifies the probability that a raw soft error finally produces a visible error in the program output. It is often used by computer designers as an important reliability metric at the architectural level. However, the AVF measurement is extremely expensive in terms of hardware and computation. In this paper, we characterize and predict a program´s AVF under resource contention and sharing with other programs running on Simultaneous Multithreading (SMT) and Chip-Multiprocessor (CMP) architectures.
Keywords :
microprocessor chips; multi-threading; parallel architectures; probability; AVF measurement; SMT/CMP architecture; architectural level; architectural vulnerability factor; chip-multiprocessor; probability; reliability metric; simultaneous multithreading; two-level soft error vulnerability prediction; visible error; Analytical models; Benchmark testing; Computer architecture; Instruction sets; Measurement; Predictive models; Training;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Workload Characterization (IISWC), 2011 IEEE International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4577-2063-5
Electronic_ISBN :
978-1-4577-2062-8
Type :
conf
DOI :
10.1109/IISWC.2011.6114203
Filename :
6114203
Link To Document :
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