Pulse arithmetic in switched capacitor neural networks

A model for a switched-capacitor neural network using pulse arithmetic is presented and its behavior is analyzed. Pulse arithmetic is used to achieve multiplication in synapses. Synapses are implemented as simple four transistor structures, suitable for VLSI fabrication, and can be made small. Both excitatory and inhibitatory synapses are possible by controlling a voltage. Multiplication can therefore be achieved by controlling both the input voltage to the switched-capacitor multiplier, and the input clock frequency. A Hopfield type associative memory is used as a basis for the analysis and simulation. Convergence issues are discussed as well as the functional operation of the system. Results of the analysis are not restricted to Hopfield type associative memories, nor to this particular switched-capacitor filter structure, but are also applicable to other types of neural networks