Low power CMOS full adder cells

Author

Sudsakorn, Attapon ; Tooprakai, Siraphop ; Dejhan, Kobchai

Author_Institution

Fac. of Eng., King Mongkut´´s Inst. of Technol. Ladkrabang, Bangkok, Thailand

fYear

2012

fDate

16-18 May 2012

Firstpage

1

Lastpage

4

Abstract

This paper presents low power CMOS full adder cells. The full adder cells are utilization to low power by using XOR and XNOR gate architectures with pass transistor logic and transmission gate. All simulation results have been carried out by using HSPICE program simulator based on 22 nm CMOS technology at 1.2 V supply voltages. The operating frequency is 250 MHz. In comparison with other 1 bit adder cells, simulation results show that have used low power consumption and power delay product of SUM and C_OUT.

Keywords

CMOS logic circuits; adders; logic gates; low-power electronics; transistor-transistor logic; CMOS technology; HSPICE program simulator; XNOR gate architectures; XOR gate architectures; frequency 250 Hz; low power CMOS full adder cells; low power consumption; pass transistor logic; size 22 nm; transmission gate; voltage 1.2 V; word length 1 bit; Adders; CMOS integrated circuits; CMOS technology; Logic gates; CMOS full adder; XNOR-XOR gate; low power full adder;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2012 9th International Conference on

Conference_Location

Phetchaburi

Print_ISBN

978-1-4673-2026-9

Type

conf

DOI

10.1109/ECTICon.2012.6254174

Filename

6254174