Hardware virtual components compliant with communication system standards

In this paper, we focus on the design of a communication system based on reusing IP cores. Traditional methods for designing hardware cores for this kind of applications use a RTL specification. However, they suffer from heavy limitations that prevent them from efficiently addressing the algorithmic complexity and the high flexibility required by the various application profiles. For this reason, we propose to raise the abstraction level of the specification and introduce the notion of architectural flexibility by benefiting from the emerging high-level synthesis tools. From a single behavioral-level VHDL specification, we are able to generate a variety of architectures, compliant with the most important communication standards. This technique has been successfully applied to the most important IP cores (synchronization IP, Viterbi IP and Reed-Solomon decoder IP cores) of the DVB-DSNG digital video-broadcasting standard.