Title :
State assignment for PAL-based CPLDs
Author :
Czerwinski, Robert ; Kania, Dariusz
Author_Institution :
Inst. of Electron., Silesian Univ. of Technol., Gliwice, Poland
fDate :
30 Aug.-3 Sept. 2005
Abstract :
In the paper, the state assignment methods of the finite state machines for PAL-based structures are presented. A main feature of the PAL-cell is a limited number of product terms (k-AND-gates) that are connected to a single sum (OR-gate). Function, which is the sum of p-implicants, when p≠k, does not take full advantage of the cell. When p>k, implementation is multi-cell (so multi-level). The main idea of solving this problem is to count the number of product terms during the process of state assignment. First algorithm leads to automata which take advantage of the number of PAL-cell terms. Second approach is dedicated to state assignment of fast automata. Methods based on primary and secondary merging conditions are presented. In one of the most basic states of the logic synthesis of sequential devices, the elements referring to restrictions of PAL-based CPLDs are taken into account.
Keywords :
finite state machines; logic design; programmable logic arrays; state assignment; CPLD; PAL; automata theory; finite state machine; logic synthesis; programmable logic arrays; sequential device; state assignment method; Automata; Automatic logic units; Encoding; Energy consumption; Flip-flops; Genetic algorithms; Information technology; Logic devices; Merging; Paper technology;
Conference_Titel :
Digital System Design, 2005. Proceedings. 8th Euromicro Conference on
Print_ISBN :
0-7695-2433-8
DOI :
10.1109/DSD.2005.71