DocumentCode :
2795644
Title :
VLSI design of a high-throughput multi-rate decoder for structured LDPC codes
Author :
Rovini, Massimo ; Insalata, Nicola E L ; Rossi, Francesco ; Fanucci, Luca
Author_Institution :
Dept. of Inf. Eng., Pisa Univ., Italy
fYear :
2005
fDate :
30 Aug.-3 Sept. 2005
Firstpage :
202
Lastpage :
209
Abstract :
Despite recent advances in the microelectronics technology, the implementation of high-throughput decoders for LDPC codes remains a challenging task. This paper aims at summarising the top-down design flow of a decoder for a structured LDPC code compliant with the WWiSE proposal for WLAN. Starting from the system performance analysis with finite-precision arithmetic, a high-throughput architecture is presented as an enhancement of the state-of-the-art solutions, and its VLSI design detailed. The envisaged architecture is also very flexible as it supports several code rates with no significant hardware overhead. The overall decoder, synthesised on 0.18μm standard cells CMOS technology, showed remarkable performances: small implementation loss (0.2dB down to BER=10-8), low latency (less than 6.0μs), high useful throughput (up to 940 Mbps) and low complexity (about 375 Kgates).
Keywords :
CMOS integrated circuits; VLSI; computational complexity; digital arithmetic; parity check codes; wireless LAN; CMOS technology; VLSI design; finite-precision arithmetic; high-throughput architecture; microelectronics technology; multirate decoder; structured LDPC codes; top-down design flow; wireless LAN; Arithmetic; CMOS technology; Decoding; Microelectronics; Parity check codes; Performance analysis; Proposals; System performance; Very large scale integration; Wireless LAN;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design, 2005. Proceedings. 8th Euromicro Conference on
Print_ISBN :
0-7695-2433-8
Type :
conf
DOI :
10.1109/DSD.2005.77
Filename :
1559801
Link To Document :
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