DocumentCode
2796629
Title
A dynamic logic circuit embedded flip-flop for ASIC design
Author
Hirairi, Koji ; Kosaka, Hideo ; Moriki, Kazutaka ; Keino, Kenji ; Onuma, Koichi
Author_Institution
Platform SOC Solution Center, SONY Corp., Tokyo, Japan
fYear
2000
fDate
2000
Firstpage
21
Lastpage
24
Abstract
We report a flip-flop with a dynamic logic circuit for data path designed with standard cell. The flip-flop provides fast logic operation by the dynamic logic circuit and reduces total power dissipation of a data path by suppressing glitches. An absolute difference unit for motion estimation is used in a benchmark test. By using the flip-flop, the unit is 20% to 40% faster and has 20% to 50% less power dissipation than when conventional D-FFs are used
Keywords
application specific integrated circuits; flip-flops; integrated logic circuits; low-power electronics; ASIC design; absolute difference unit; complex logic function; dynamic logic circuit embedded flip-flop; glitch suppression; motion estimation; standard cell designed data path; total power dissipation; Application specific integrated circuits; Clocks; Delay; Flip-flops; Latches; Logic circuits; Logic functions; MOS devices; Power dissipation; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location
Cheju
Print_ISBN
0-7803-6470-8
Type
conf
DOI
10.1109/APASIC.2000.896898
Filename
896898
Link To Document