The non-full voltage swing TSPC (NSTSPC) logic design

Author

Cheng, Kuo-Hsing ; Huang, Yung-Chong

Author_Institution

Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan

fYear

2000

fDate

2000

Firstpage

37

Lastpage

40

Abstract

In this paper, a new TSPC logic circuit is proposed for low-voltage high-speed applications. The proposed new circuit using non-full voltage swing scheme in internal nodes to reduce logic evaluation time and to save dynamic power. Thus the advantages of the new TSPC logic circuit over the conventional TSPC logic circuit are speed and power-delay product. Based upon the 0.35 μm CMOS technology, the proposed new TSPC logic has 25% improvement over the conventional TSPC circuit in power-delay product. The new circuit can be operated at 250 MHz with 1.2 V supply voltage

Keywords

CMOS logic circuits; delays; high-speed integrated circuits; integrated circuit design; logic design; low-power electronics; 0.35 micron; 1.2 V; 250 MHz; CMOS technology; LV operation; high-speed applications; low-voltage applications; non-full voltage swing TSPC logic design; power-delay product; true single phase clock logic; CMOS logic circuits; CMOS technology; Clocks; Latches; Logic circuits; Logic design; Logic gates; MOS devices; MOSFETs; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896902

Filename

896902