A self-timed wave pipelined adder using data align method

Author

Lim, Byoung-Hoon ; Kang, Jin-Ku

Author_Institution

Dept. of Electr. & Comput. Eng., Inha Univ., Inchon, South Korea

fYear

2000

fDate

2000

Firstpage

77

Lastpage

80

Abstract

A 32 bit wave pipelined adder circuitry using static CMOS plus data aligning logic is presented. The self-timed wave pipelining algorithm was implemented in the circuit design. The data aligning logic in the algorithm consisted of the double edge triggered flip-flop detecting the slowest arrived signal, the aligning signal generator and latches. Using the algorithm, the delay variation of the signals at the output of the 32 bit adder could be controlled under 130 ps rather than 766 ps in a conventional adder. The circuit operates at a data rate of 800 M/bps using 0.25 μm CMOS technology with a 2.5 V supply voltage

Keywords

CMOS logic circuits; adders; delays; flip-flops; pipeline arithmetic; timing; 0.25 mum; 2.5 V; 32 bit; 800 Mbit/s; CMOS technology; aligning signal generator; circuit design; data aligning logic; data rate; double edge triggered flip-flop; latches; self-timed wave pipelined adder; self-timed wave pipelining algorithm; signal delay variation; static CMOS logic; supply voltage; Adders; CMOS logic circuits; CMOS technology; Circuit synthesis; Delay; Flip-flops; Latches; Pipeline processing; Signal generators; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896912

Filename

896912