DocumentCode
2796968
Title
A low-power 1.2 GHz 0.35 μm CMOS PLL
Author
Juang, Dar-Chang ; Chen, De-Sheng ; Shyu, Jyuo-Min ; Wu, Ching-Yuang
Author_Institution
Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2000
fDate
2000
Firstpage
99
Lastpage
102
Abstract
In this paper, a low-power high-speed CMOS PLL is presented. The PLL consists of a 1.2-GHz voltage controlled oscillator, a dead-zone free phase frequency detector, a charge pump, and a frequency divider. The circuit was fabricated using 0.35 μm TSMC CMOS technology. The total power consumption is 9.6 mW at 1.2-GHz operating frequency with 1.5 V supply voltage. The phase noise is -94 dBc at 10 kHz offset
Keywords
CMOS integrated circuits; UHF integrated circuits; application specific integrated circuits; detector circuits; high-speed integrated circuits; low-power electronics; phase locked loops; 0.35 micron; 1.2 GHz; 1.5 V; 9.6 mW; TSMC CMOS technology; charge pump; dead-zone free phase frequency detector; frequency divider; high-speed CMOS PLL; low-power CMOS PLL; phase noise; voltage controlled oscillator; CMOS technology; Charge pumps; Circuits; Energy consumption; Frequency conversion; Phase frequency detector; Phase locked loops; Phase noise; Voltage; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location
Cheju
Print_ISBN
0-7803-6470-8
Type
conf
DOI
10.1109/APASIC.2000.896918
Filename
896918
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