A novel FPGA design of a wireless block transmission channel equalizer

In this paper a novel block transmission decision feedback equalizer (DFE) design suitable for hardware (VLSI/FPGA) implementation was proposed. Our DFE design is based on Cholesky factorization, which is used to define a noise whitener and a maximum-likelihood block detector. The Schur algorithm, employed for solving the Cholesky factorization, cannot only reduce the computational complexity but also facilitate the computing concurrency. The derived decision-feedback equalizer design features a highly parallel, hardware efficient and scalable design. In our design example with a wireless channel, the proposed design, implemented in one Xilinx Virtex XCV 300-6 FPGA, is capable of operating at a clock rate up to 36 MHz and achieving a processing rate as high as 3 million symbols update per second