Title :
Analysis and implementation of interface for heterogeneous system
Author :
Jung, Hwi-Sung ; Lee, Moon-Key
Author_Institution :
Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
We designed asynchronous event logic library with 0.25 μm CMOS technology and high-speed asynchronous FIFO operating at 1.6 GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for freeing of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, we implemented high-speed 32 bit-interface chip for heterogeneous system. The size of the core is about 1.1 mm×1.1 mm
Keywords :
CMOS logic circuits; asynchronous circuits; asynchronous sequential logic; clocks; hardware description languages; high-speed integrated circuits; logic CAD; 0.25 micron; 1.6 GHz; 32 bit; CMOS technology; Verilog models; asynchronous event logic library; asynchronous standard cell layouts; clock control circuit; clock skew; design bottleneck; heterogeneous system; high-speed asynchronous FIFO; synchronization failures; top-down design methodology; CMOS logic circuits; CMOS technology; Clocks; Communication system control; Design methodology; Design optimization; Hardware design languages; Libraries; Logic design; Semiconductor device modeling;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896930
