Static-based verification of memory BIST integration

Static-based verification methodologies are employed to minimize iterative simulations due to functional and timing problems after BIST integration into an ASIC. Formal equivalence checking is used to verify if BIST signals are correctly integrated into an ASIC. Static Timing Analysis (STA) is used to verify BIST timing. Two ASICs, implemented using 0.25 μm technology, are used to apply static-based verification methodologies. Our experimental results show that static-based verification achieves significant verification speedup compared to simulation. This allows fast and early detection of function and timing errors that may be introduced during BIST integration: