Design of an equalizer using the DFE structure and the MMA algorithm

Author

Shin, DaeKyo ; Hwang, Seung Joong ; Jo, Byoung Gak ; Sunwoo, Myung H.

Author_Institution

Dept. of Electron. Eng., Ajou Univ., Suwon, South Korea

fYear

2000

fDate

2000

Firstpage

195

Lastpage

198

Abstract

This paper proposes an equalizer using MMA (MultiModulus Algorithm) and LMS (Least Mean Square) algorithms and uses a DFE (Decision Feedback Equalizer) structure. The existing MMA equalizer uses two transversal filters but the proposed equalizer uses two DFE filter banks to improve the channel adaptive performance and to reduce the number of taps. The fabricated equalizer ASIC chip using the MMA and LMS algorithms operates at 8 MHz and provides 64 Mbps which is higher than existing equalizers. The chip uses the 0.35 μm technology and has about 160000 gates

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; decision feedback equalisers; digital signal processing chips; least mean squares methods; 0.35 micron; 64 Mbit/s; 8 MHz; CMOS technology; DFE filter banks; DFE structure; LMS algorithm; MMA algorithm; channel adaptive performance; decision feedback equalizer; equalizer ASIC chip; equalizer design; least mean square algorithm; multimodulus algorithm; Adaptive algorithm; Algorithm design and analysis; Bit error rate; Constellation diagram; DSL; Decision feedback equalizers; Least squares approximation; Probability distribution; Steady-state; Transversal filters;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896942

Filename

896942