Efficient simultaneous rounding method removing sticky-bit from critical path for floating point addition

Processing flow of the conventional floating point addition/subtraction operation consists of several steps, i.e., alignment, addition/subtraction, normalization, and rounding stages in this order. A floating adder/subtractor performing addition/subtraction and IEEE rounding in parallel was presented where any additional execution time nor any high speed adder for rounding operation was not required. But, the sticky-bit, which is generated at the alignment stage, is included in the critical path delay. In this research, a technique to remove the sticky-bit generation from the critical path is proposed. Its hardware model and correctness proofs are provided and evaluated. The proposed floating point adder provides effectiveness in the points of chip area and its execution time