Title :
An efficient system to develop various soft IPs
Author :
Bae, Jong-Hong ; Kyung, Seong Jun ; Ahn, Mun-Won ; Kim, Seong-Sik ; Lim, Ji-Soo ; Cha, Wook-Jin ; Lee, Jong-Oh ; Kwon, Ho-Kyeong ; Yoo, Se-Jin ; Cho, Dong-Soo ; Chae, Jay
Author_Institution :
Hyundai Electron. Ind. Co. Ltd., Seoul, South Korea
Abstract :
Evolutional enhancement in VLSI technology makes a complicated system integrated in a chip. To design a system with large complexity, well-designed macro block, IP (Intellectual Property), is preferred to reduce design time enormously. A system, named ART (automatic RTL translation), is developed to generate synthesizable RTL IPs from legacy hard macros. With help of the ART system, we developed a soft IP of an 8-bit embedded microcontroller. The operating frequency of the IP is up to 80 MHz with a 0.6 μm CMOS technology. An MCU for Digital Tuning System (DTS) was also developed using the IP with the same technology
Keywords :
CMOS digital integrated circuits; VLSI; application specific integrated circuits; formal verification; high level synthesis; industrial property; integrated circuit design; microcontrollers; 0 to 80 MHz; 0.6 micron; 8 bit; ART; CMOS technology; Digital Tuning System; MCU; VLSI technology; automatic RTL translation; design time; embedded microcontroller; legacy hard macros; macro block; operating frequency; soft IPs; Automatic control; CMOS technology; Control system synthesis; Frequency; Hardware design languages; Intellectual property; Logic; Subspace constraints; System-on-a-chip; Tuning;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896951
