AE32000: an embedded microprocessor core

Author

Oh, H.-C. ; Kim, H.-G. ; Jung, H.-S. ; Lee, J.-W. ; Kim, B.-J. ; Jung, J.-Y. ; Min, B.-G. ; Lim, J.-Y. ; Lee, H. ; Kwon, K.-H.

Author_Institution

Sch. of Eng., Korea Univ., Seoul, South Korea

fYear

2000

fDate

2000

Firstpage

255

Lastpage

258

Abstract

The ADC´s EISC microprocessor family has been developed to address the need for reduction in the amount of memory access of today´s embedded applications. In this paper, we introduce the microarchitecture of the AE32000 processor, a 32-bit member of the ADC´s EISC family. Specifically, we discuss the pipelining scheme and LERI-instruction folding, and we present the performance of our current implementation. We also introduce a system implementation utilizing the AE32000 processor

Keywords

CMOS digital integrated circuits; computer architecture; embedded systems; microcontrollers; microprocessor chips; performance evaluation; pipeline processing; 32 bit; AE32000 microprocessor core; EISC microprocessor family; LERI-instruction folding; VISA2000 microcontroller; embedded microprocessor core; memory access reduction; microarchitecture; pipelining scheme; system implementation; Asia; Data processing; Delay; Embedded system; Emulation; Microarchitecture; Microprocessors; Pipeline processing; Reduced instruction set computing; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896957

Filename

896957