An efficient implementation of BIST for floating point DSP processor

Author

Park, Jaeheung ; Chang, Hoon ; Song, Ohyoung

Author_Institution

Dept. of Comput., Soongsil Univ., South Korea

fYear

2000

fDate

2000

Firstpage

273

Lastpage

276

Abstract

In this paper, we describe the implementation of BIST technique which is applied to enhance the reliability of the FLOVA chip i.e., the floating point DSP core for processing graphic data and 3D graphics. In order to enhance the reliability of FLOVA, we adopt the BIST technique for floating-point modules which have complicated logic. For embedded data and program memory, we adopt the memory BIST technique. The boundary scan technique, providing board-level testing and to control BIST logic, has been also implemented

Keywords

automatic test pattern generation; boundary scan testing; built-in self test; computer graphic equipment; design for testability; digital signal processing chips; floating point arithmetic; integrated circuit reliability; integrated circuit testing; logic testing; 3D graphics; ATPG; BIST logic; DFT; FLOVA chip; board-level testing; boundary scan technique; efficient BIST implementation; embedded data memory; embedded program memory; floating point DSP processor; graphic data processing; memory BIST technique; reliability; Automatic testing; Built-in self-test; Design for testability; Digital signal processing; Digital signal processing chips; Graphics; Logic testing; Registers; VLIW; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896961

Filename

896961