DocumentCode :
2797656
Title :
Test methodology for low power SRAM´s (Is Iddq test useful for low power SRAM´s?)
Author :
Suh, Ilseok ; Kim, Hong-Sik ; Kang, Sungho ; Han, Gunhee
Author_Institution :
Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea
fYear :
2000
fDate :
2000
Firstpage :
277
Lastpage :
280
Abstract :
The increase in integrity of the recent VLSI technology has enabled a trend of small and portable applications. These portable applications, like notebook computers and cellular phones, need the high-performance and low-power consumption. In most products the major power consuming elements are the memories. So low power memory technology has been developed. But the test features have not been studied sufficiently. This paper provides a test methodology useful for low power SRAM´s. Also simulation results for the Driving Source Line technology show how useful the Iddq test is
Keywords :
SRAM chips; VLSI; integrated circuit testing; logic testing; low-power electronics; Iddq test; VLSI technology; driving source line architecture; low power SRAM; low power memory technology; low-power consumption; portable applications; test features; test methodology; Application software; Circuit faults; Circuit testing; DSL; Delay effects; Energy consumption; Low voltage; MOSFET circuits; Random access memory; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
Type :
conf
DOI :
10.1109/APASIC.2000.896962
Filename :
896962
Link To Document :
بازگشت