Testability strategy and DFT methodology of CalmRISC32

Author

Kim, Hong-Sik ; Seo, Il Seok ; Kang, Sungho ; Han, Gunhee

Author_Institution

Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea

fYear

2000

fDate

2000

Firstpage

295

Lastpage

298

Abstract

This paper describes the test strategy and the DFT (Design for Testability) methodology of CalmRISC32. CalmRISC32 is a 32 bit microcontrol unit, which consists of a 32 bit IU core, an FPU and a Cache Unit. The embedded memory arrays are tested by memory BIST (Built-in Self Test) and the logic blocks are tested by functional test methodology at the instruction level. To increase the test efficiency, a new scan chain methodology using a module called a TSU (Test Scan Unit) is developed

Keywords

boundary scan testing; built-in self test; design for testability; logic testing; microcontrollers; pipeline processing; reduced instruction set computing; 32 bit; CalmRISC32; DFT methodology; FPU; IU core; TSU; cache unit; embedded memory arrays; functional test methodology; instruction level; memory BIST; microcontrol unit; scan chain methodology; test efficiency; test scan unit; testability strategy; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design for testability; Hardware; Logic arrays; Logic testing; Microprocessors; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896966

Filename

896966