Transition count based BIST for detecting multiple stuck-open faults in CMOS circuits

Author

Rahaman, Hafizur ; Das, Debesh K. ; Bhattacharya, Bhargab B.

Author_Institution

Dept. of Comput. Sci. & Tech., APC Roy Polytech. Coll., Calcutta, India

fYear

2000

fDate

2000

Firstpage

307

Lastpage

310

Abstract

This paper presents a BIST design suitable for detecting multiple stuck-open faults in two-level CMOS single complex cells. The test pattern generator (TPG) generates a sequence of length 2n.2ⁿ that includes all n.2ⁿ single-input-change (SIC) ordered test pairs for an n-input circuit under test (CUT). The signature analyzer (SA) counts the number of alternate transitions at the output. Design of the corresponding TPG and SA is straightforward

Keywords

CMOS logic circuits; automatic test pattern generation; built-in self test; cellular arrays; combinational circuits; fault diagnosis; integrated circuit testing; logic analysers; CMOS circuits; alternate transitions; combinational circuits; multiple stuck-open faults; n-input circuit under test; signature analyzer; single-input-change ordered test pairs; test pattern generator; transition count based BIST; two-level CMOS single complex cells; Built-in self-test; Circuit faults; Circuit testing; Clocks; Delay; Electrical fault detection; Fault detection; Robustness; Silicon carbide; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896969

Filename

896969