The cache memory system for CalmRISC32

Author

Lee, Kil-Whan ; Lee, Jang-Soo ; Park, Gi-Ho ; Lee, Jung-Hoon ; Han, Tack-Don ; Kim, Shin-Dug ; Kim, Yong-Chun ; Jung, SehWoong ; Lee, Kwang-Yup

Author_Institution

Dept. of Comput. Sci., Yonsei Univ., Seoul, South Korea

fYear

2000

fDate

2000

Firstpage

323

Lastpage

326

Abstract

The cache memory system for CalmRISC32 embedded processor is described in this paper. A dual data cache system structure called a cooperative cache that takes advantage of design flexibilities of a dual cache structure is used as the cache memory system for CalmRISC32 to improve performance and reduce power consumption. The cooperative cache system is applied to both data cache and instruction cache. This paper describes the structure and operational model of the cache memory system for CalmRISC32. The implementation of the cache memory system for CalmRISC32 is also presented

Keywords

cache storage; memory architecture; microprocessor chips; reduced instruction set computing; 32 bit; CalmRISC32; cache memory system; cooperative cache; data cache; design flexibilities; dual data cache system structure; embedded processor; instruction cache; operational model; power consumption; Bandwidth; Cache memory; Computer science; Cooperative caching; Deductive databases; Embedded computing; Energy consumption; Large scale integration; Power system modeling; Spatial resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896973

Filename

896973