Title :
The design and implementation of CalmlRISC32 floating point unit
Author :
Jeong, Cheol-ho ; Park, Woo-Chan ; Kim, Sang-Woo ; Han, Tack-Don
Author_Institution :
Dept. of Comput. Sci., Yonsei Univ., Seoul, South Korea
Abstract :
The CalmRISC32 FPU is RISC style coprocessor for embedded systems. It supports IEEE-754 standard single precision addition/subtraction, floating-point multiplication, floating-point division, format conversion, comparison, rounding, and load/store. It also supports four rounding modes, and precise exception. It can execute and complete instructions out of order if some constraint is resolved-data dependency, resource conflict, and exception prediction. Standard cell base design technique is used to save design time and cost. First prototype is running at about 70 Mhz with worst-case delay in gate level simulation
Keywords :
IEEE standards; coprocessors; floating point arithmetic; integrated circuit design; pipeline processing; reduced instruction set computing; 32 bit; 70 MHz; CalmlRISC32; IEEE-754 standard single precision addition/subtraction; RISC style coprocessor; comparison; data dependency; embedded systems; exception prediction; floating point unit; floating-point division; floating-point multiplication; format conversion; gate level simulation; precise exception; resource conflict; rounding modes; standard cell base design; worst-case delay; Computer science; Coprocessors; Costs; Delay; Embedded system; Floating-point arithmetic; Hardware; Out of order; Pipelines; Reduced instruction set computing;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896974
