A 4-way VLIW embedded processor and its companion chip

Author

Hirose, Y. ; Saito, M. ; Utsumi, H. ; Saruwatari, T. ; Suga, A. ; Sukemura, T. ; Takahashi, H. ; Miyake, H. ; Takebe, Y. ; Kimura, M. ; Okano, H. ; Tsuji, M. ; Satoh, T. ; Katayama, T.

Author_Institution

Fujitsu Labs. Ltd., Kawasaki, Japan

fYear

2000

fDate

2000

Firstpage

363

Lastpage

366

Abstract

A 4-way VLIW microprocessor based on an improved VLIW architecture is developed for embedded application in a 0.18 μm 5-layer-metal CMOS process. This processor equips a 2-way integer pipeline and a 2-way floating/media pipeline. Each floating pipeline and media pipeline has 2-parallel and 4-parallel SIMD mechanisms, respectively. The processor equips separate instruction and data caches; each of 16 KB size and 4-way set associative. 6.7 M transistors are integrated in an area of 7.5 mm×7.5 mm. We also developed companion chip which is used together with the processor. Companion chip is fabricated using a 0.25 μm 4-layer-metal CMOS process

Keywords

CMOS digital integrated circuits; VLSI; cache storage; content-addressable storage; high-speed integrated circuits; microprocessor chips; parallel architectures; pipeline processing; 0.18 micron; 0.25 micron; 133 MHz; 16 KB; 2-way floating/media pipeline; 2-way integer pipeline; 266 MHz; 4-layer-metal CMOS process; 4-way VLIW embedded processor; 4-way set associative cache; SIMD mechanisms; VLIW architecture; companion chip; data cache; embedded application; five-layer-metal CMOS process; instruction cache; CMOS process; Delay; Digital signal processing chips; Electronic mail; Laboratories; Microprocessors; Pipelines; SDRAM; Switches; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896984

Filename

896984