VLSI architectures for Viterbi decoding

The computational complexity of the Viterbi algorithm and its storage requirements are proportional to the number of states in the underlying model. Unfortunately the number of states grows exponentially as the number of transmitted symbols influencing a received symbol is increased and hence the algorithm soon becomes impractical using conventional implementation methods. The paper describes three VLSI architectures for performing the Viterbi algorithm and discusses their relative merits. The authors´ interest in studying architectures is to find solutions which result in small silicon areas and low power consumption. Where these two goals cannot be satisfied together they have concentrated on achieving lower power. They feel this is justified since future advances in VLSI technology will reduce device area more than they will reduce power consumption. In addition the rate of advance in VLSI technology is greater than the rate of advance in battery technology which might otherwise obviate the need for low power consumption