Cycle efficient scrambler implementation for software defined radio

The task of efficient implementation of bit-serial scrambler algorithms on a word-parallel software defined radio micro-architecture is considered. By exploiting properties of the exclusive-OR Boolean logic operator, a novel power-of-two look-ahead recursive algorithm transformation method is developed. Together with loop-unrolling, this new method produces an efficient vector scrambler algorithm formulation that realizes orders of magnitude clock-cycle savings compared to state of the art solutions. Using IEEE 802.11a scrambler algorithm as an example, this new formulation is 9 times faster than previously reported results.