How to improve the silicon nanocrystal memory cell performances for low power applications

Author

Della Marca, V. ; Amouroux, J. ; Molas, G. ; Postel-Pellerin, J. ; Lalande, F. ; Boivin, P. ; Jalaguier, E. ; De Salvo, B. ; Ogier, J.

Author_Institution

STMicroelectron., Rousset, France

Volume

1

fYear

2012

fDate

15-17 Oct. 2012

Firstpage

103

Lastpage

106

Abstract

In this paper we propose to optimize the 1T silicon nanocrystal (Si-nc) memory cell in order to reduce the energy consumption for low power applications. Optimized Channel Hot Electron Injection (a 4.5V programming window is reached consuming 1nJ) and Fowler-Nordheim programming are analyzed and compared. The tunnel oxide thickness, Si-ncs area coverage and SiN silicon nanocrystals capping layer are adjusted to optimize the data retention and endurance criteria. We present for the first time the endurance characteristics of a Si-nc cell up to 10⁶ cycles with a final programming window of 4V.

Keywords

elemental semiconductors; energy consumption; flash memories; hot carriers; low-power electronics; nanostructured materials; silicon; tunnelling; 1T silicon nanocrystal memory cell performance; Fowler-Nordheim programming; Si; data retention; endurance criteria; energy consumption; flash memory; low power application; nanocrystals capping layer; optimized channel hot electron injection; programming window; tunnel oxide thickness; voltage 4.5 V; Computer architecture; Microprocessors; Nanocrystals; Nonvolatile memory; Programming; Silicon; Silicon compounds; Silicon nanocrystal memories; energy consumption; tunnel oxide thickness;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference (CAS), 2012 International

Conference_Location

Sinaia

ISSN

1545-857X

Print_ISBN

978-1-4673-0737-6

Type

conf

DOI

10.1109/SMICND.2012.6400686

Filename

6400686