On Generating Vectors for Accurate Post-Silicon Delay Characterization

In this paper, we propose a new method to generate vectors for post-silicon delay characterization, especially for exposing delay marginalities during post-silicon validation and speed binning during testing. Our method generates vectors that are guaranteed to excite the worst-case delays of fabricated chips without introducing any pessimism. It embodies several innovations, including a resilient gate delay model that captures multiple input switching effects and process variations, new conditions that vectors must satisfy to invoke the maximum delay of a target path, and a new approach to generate multiple vectors (vector-spaces) that are collectively guaranteed to invoke the worst-case delay of the target path. We present experimental results for benchmark circuits to demonstrate the effectiveness of our method for post-silicon validation and describe how the generated vectors can be adapted for speed binning.